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Noté. / 5. Basé sur avis des utilisateurs
Low Voltage Intel
®
Xeon
™
Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz
64 Datasheet
Reserved AD29 Reserved Reserved
Reserved AE15 Reserved Reserved
Reserved AE16 Reserved Reserved
RESET# Y8
Common
Clk
Input
RS0# E21
Common
Clk
Input
RS1# D22
Common
Clk
Input
RS2# F21
Common
Clk
Input
RSP# C6
Common
Clk
Input
SKTOCC# A3 Power/Other Output
SLP# AE6 Async GTL+ Input
SMI# C27 Async GTL+ Input
STPCLK# D4 Async GTL+ Input
TCK E24 TAP Input
TDI C24 TAP Input
TDO E25 TAP Output
TESTHI0 W6 Power/Other Input
TESTHI1 W7 Power/Other Input
TESTHI2 W8 Power/Other Input
TESTHI3 Y6 Power/Other Input
TESTHI4 AA7 Power/Other Input
TESTHI5 AD5 Power/Other Input
TESTHI6 AE5 Power/Other Input
THERMDA Y27 Anode Pin Output
THERMDC Y28 Cathode Pin Output
THERMTRIP# F26 Async GTL+ Output
TMS A25 TAP Input
TRDY# E19
Common
Clk
Input
TRST# F24 TAP Input
VCC A2 Power/Other
VCC A8 Power/Other
VCC A14 Power/Other
VCC A18 Power/Other
VCC A24 Power/Other
Table 34. Pin Listing by Pin Name
Pin Name Pin No.
Signal
Buffer Type
Direction
VCC A28 Power/Other
VCC A30 Power/Other
VCC B4 Power/Other
VCC B6 Power/Other
VCC B12 Power/Other
VCC B20 Power/Other
VCC B26 Power/Other
VCC B29 Power/Other
VCC B31 Power/Other
VCC C2 Power/Other
VCC C4 Power/Other
VCC C10 Power/Other
VCC C16 Power/Other
VCC C22 Power/Other
VCC C28 Power/Other
VCC C30 Power/Other
VCC D1 Power/Other
VCC D8 Power/Other
VCC D14 Power/Other
VCC D18 Power/Other
VCC D24 Power/Other
VCC D29 Power/Other
VCC D31 Power/Other
VCC E2 Power/Other
VCC E6 Power/Other
VCC E12 Power/Other
VCC E20 Power/Other
VCC E26 Power/Other
VCC E28 Power/Other
VCC E30 Power/Other
VCC F1 Power/Other
VCC F4 Power/Other
VCC F10 Power/Other
VCC F16 Power/Other
VCC F22 Power/Other
VCC F29 Power/Other
VCC F31 Power/Other
Table 34. Pin Listing by Pin Name
Pin Name Pin No.
Signal
Buffer Type
Direction
- Low Voltage Intel 1
- Processor at 1
- 1.60 GHz, 2.0 GHz and 2.4 GHz 1
- 2 Datasheet 2
- Contents 3
- Revision History 7
- 8 Datasheet 8
- 1.0 Introduction 9
- 1.1 Terminology 10
- 1.2 State of Data 11
- 1.3 References 11
- 12 Datasheet 12
- 2.0 Electrical Specifications 13
- Decoupling 14
- 2.5 PLL Filter 15
- Figure 1. Typical V 16
- Power Distribution 16
- 2.6 Voltage Identification 17
- 18 Datasheet 18
- 2.7 Reserved Or Unused Pins 19
- 2.8 System Bus Signal Groups 19
- 20 Datasheet 20
- 2.9 Asynchronous GTL+ Signals 21
- 2.10 Maximum Ratings 21
- 22 Datasheet 22
- Datasheet 23 23
- Figure 3. Low Voltage Intel 24
- Processor Voltage and 24
- Datasheet 25 25
- 26 Datasheet 26
- Datasheet 27 27
- 28 Datasheet 28
- Datasheet 29 29
- 30 Datasheet 30
- Datasheet 31 31
- 32 Datasheet 32
- Datasheet 33 33
- 34 Datasheet 34
- Datasheet 35 35
- 36 Datasheet 36
- Figure 15. THERMTRIP# to V 37
- Power Down 38
- Power Up 38
- Datasheet 39 39
- 40 Datasheet 40
- Noise Margi 41
- 42 Datasheet 42
- Datasheet 43 43
- 3.3.4 Activity Factor 44
- Specifications 45
- 46 Datasheet 46
- Datasheet 47 47
- 48 Datasheet 48
- Undershoot Tolerance 49
- 50 Datasheet 50
- 4.0 Mechanical Specifications 51
- 4.1 Mechanical Specifications 52
- Figure 25. Low Voltage Intel 53
- 54 Datasheet 54
- Datasheet 55 55
- 56 Datasheet 56
- 4.3 Insertion Specifications 57
- 4.4 Mass Specifications 57
- 4.5 Materials 57
- 4.6 Markings 58
- 4.7 Processor Pin-Out Diagram 58
- Datasheet 59 59
- 60 Datasheet 60
- 5.1 Processor Pin Assignments 61
- 62 Datasheet 62
- Datasheet 63 63
- 64 Datasheet 64
- Datasheet 65 65
- 66 Datasheet 66
- Datasheet 67 67
- 68 Datasheet 68
- Datasheet 69 69
- 70 Datasheet 70
- Datasheet 71 71
- 72 Datasheet 72
- Datasheet 73 73
- 74 Datasheet 74
- Datasheet 75 75
- 76 Datasheet 76
- Datasheet 77 77
- 78 Datasheet 78
- 5.2 Signal Definitions 79
- 80 Datasheet 80
- 82 Datasheet 82
- Datasheet 83 83
- 84 Datasheet 84
- Datasheet 85 85
- 86 Datasheet 86
- Datasheet 87 87
- 88 Datasheet 88
- 6.0 Thermal Specifications 89
- 90 Datasheet 90
- Datasheet 91 91
- 92 Datasheet 92
- 7.0 Features 93
- 94 Datasheet 94
- 7.2.5 Sleep State—State 5 95
- 7.3 Thermal Monitor 96
- 7.4 Thermal Diode 97
- 98 Datasheet 98
- Debug Port Design Guide 99
- 100 Datasheet 100
- 9.0 Appendix A 101
- 102 Datasheet 102
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