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Low Voltage Intel

Xeon

™

Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz

Datasheet 31

2.14 Processor AC Timing Waveforms

The following figures are used in conjunction with the AC timing tables, Table 12 through Table

18.

Note: For Figure 5 through Figure 14, the following apply:

1. All common clock AC timings for AGTL+ signals are referenced to the Crossing Voltage

CROSS

) of the BCLK[1:0] at rising edge of BCLK0. All common clock AGTL+ signal

timings are referenced at GTLREF at the processor core (pads).

2. All source synchronous AC timings for AGTL+ signals are referenced to their associated

strobe (address or data) at GTLREF. Source synchronous data signals are referenced to the

Table 17. System Bus AC Specifications (Reset Conditions)

T# Parameter Min Max Unit Figure Notes

T45: Reset Configuration Signals (A[31:3]#, BR0#, INIT#,

SMI#) Setup Time

4BCLKs11 1

T46: Reset Configuration Signals (A[31:3]#, INIT#, SMI#)

Hold Time

220BCLKs11 2

T47: Reset Configuration Signal BR0# Hold Time 2 2 BCLKs 11 2

NOTES:

1. Before the de-assertion of RESET#

2. After the clock that de-asserts RESET#

Table 18. TAP Signal Group AC Specifications

T# Parameter Min Max Unit Figure Notes1

T55: TCK Period 60.0 ns 5

T56: TCK Rise Time 9.5 ns 53

T57: TCK Fall Time 9.5 ns 53

T58: TMS, TDI Rise Time 8.5 ns 53

T59: TMS, TDI Fall Time 8.5 ns 53

T61: TDI, TMS Setup Time 0 ns 13 4, 6

T62: TDI, TMS Hold Time 3.0 ns 13 4, 6

T63: TDO Clock to Output Delay 0.5 3.5 ns 13 5

T64: TRST# Assert Time 2.0 T

TCK

14 7

NOTES:

1. Not 100% tested. Specified by design characterization.

2. All AC timings for the TAP signals are referenced to the TCK signal at 0.5 * V

at the processor pins. All

TAP signal timings (TMS, TDI, etc) are referenced at the 0.5 * V

processor pins.

3. Rise and fall times are measured from the 20% to 80% points of the signal swing.

4. Referenced to the rising edge of TCK.

5. Referenced to the falling edge of TCK.

6. Specification for a minimum swing defined between TAP 20% to 80%. This assumes a minimum edge rate

of 0.5 V/ns.

7. TRST# must be held asserted for two TCK periods to ensure recognition by the processor.

8. It is recommended that TMS be asserted while TRST# is being deasserted

1 2 ... 26 27 28 29 30 31 32 33 34 35 36 ... 101 102

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