Low Voltage Intel
®
Xeon
™
Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz
34 Datasheet
Figure 8. System Bus Common Clock Valid Delay Timing Waveform
Figure 9. System Bus Source Synchronous 2X (Address) Timing Waveform
BCLK0
BCLK1
Common Clock
Signal (@ driver)
Common Clock
Signal (@ receiver)
T0
T1 T2
T
Q
T
R
valid valid
valid
T
P
T
P
= T10: Common Clock Output Valid Delay
T
Q
= T11: Common Clock Input Setup
T
R
= T12: Common Clock Input Hold Time
T
J
BCLK0
BCLK1
ADSTB# (@ driver)
A# (@ driver)
A# (@ receiver)
ADSTB# (@ receiver)
T1 T2
1/4
BCLK
1/2
BCLK
3/4
BCLK
T
H
T
H
T
J
T
N
T
K
T
M
valid valid
valid
valid
T
H
= T23: Source Sync. Address Output Valid Before Address Strobe
T
J
= T24: Source Sync. Address Output Valid After Address Strobe
T
K
= T27: Source Sync. Input Setup to BCLK
T
M
= T26: Source Sync. Input Hold Time
T
N
= T25: Source Sync. Input Setup Time
T
P
= T28: First Address Strobe to Second Address Strobe
T
S
= T20: Source Sync. Output Valid Delay
T
R
= T31: Address Strobe Output Valid Delay
T
P
T
R
T
S
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