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Low Voltage Intel

Xeon

™

Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz

20 Datasheet

rising edge of BCLK0. Asynchronous signals are still present (A20M#, IGNNE#, etc.) and may

become active at any time during the clock cycle. Table 5 identifies which signals are common

clock, source synchronous and asynchronous.

Table 5. System Bus Signal Groups

Signal Group Type Signals

AGTL+ Common Clock Input Synchronous to BCLK[1:0]

BPRI#, BR[3:1]#

3, 4

, DEFER#, RESET#

RS[2:0]#, RSP#, TRDY#

AGTL+ Common Clock I/O Synchronous to BCLK[1:0]

ADS#, AP[1:0]#, BINIT#

, BNR#

, BPM[5:0]#

BR0#

, DBSY#, DP[3:0]#, DRDY#, HIT#

HITM#

, LOCK#, MCERR#

AGTL+ Source Synchronous

I/O

Synchronous to assoc.

strobe

AGTL+ Strobes Synchronous to BCLK[1:0] ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#

Asynchronous GTL+ Input

Asynchronous

A20M#

, IGNNE#

, INIT#

, LINT0/INTR

LINT1/NMI

, SMI#

, SLP#, STPCLK#

Asynchronous GTL+ Output

Asynchronous FERR#, IERR#, THERMTRIP#

Asynchronous GTL+ Input/

Output

Asynchronous PROCHOT#

System Bus Clock Clock BCLK1, BCLK0

TAP Input

Synchronous to TCK TCK, TDI, TMS, TRST#

TAP Output

Synchronous to TCK TDO

Power/Other Power/Other

BSEL[1:0], COMP[1:0], GTLREF, ODTEN,

Reserved, SKTOCC#, TESTHI[6:0],VID[4:0],

, V

CCA

, V

CCIOPLL

, V

SSA

, V

CCSENSE

SSSENSE,

PWRGOOD, THERMDA,

THERMDC. VID_V

NOTES:

1. Refer to Section 5.2 for signal descriptions.

2. These AGTL+ signal groups are not terminated by the processor. Refer the ITP700 Debug Port Design

Guide and corresponding Design Guide for termination requirements and further details.

3. The Low Voltage Intel

Xeon™ processor utilizes only BR0# and BR1#. BR2# and BR3# are not driven by

the processor but must be terminated to V

. For additional details regarding the BR[3:0]# signals, see

Section 5.2 and Section 7.1 and the appropriate Platform Design Guidelines.

4. These signal groups are not terminated by the processor. Refer to the appropriate platform design

guidelines and the ITP700 Debug Port Design Guide for termination recommendations.

5. The volume on these pins during active-to-inactive edge of RESET# determines the multiplier that the

Phase Lock Loop (PLL) will use for internal core clock

6. The value of these pins during the active-to-inactive edge of RESET# to determine processor configuration

options. See Section 7.1 for details.

7. These signals may be driven simultaneously by multiple agents (wired-OR).

8. VID_V

is required for correct operation of the Low Voltage Intel

Xeon™ Processor. Refer to Figure 16

for details.

9. It is an output only on the 1.60 GHz Low Voltage Intel

Xeon™ processor with CPUID of 0F27h.

Signals Associated Strobe

REQ[4:0]#,A[16:3]#

ADSTB0#

A[35:17]#

ADSTB1#

D[15:0]#, DBI0# DSTBP0#, DSTBN0#

D[31:16]#, DBI1# DSTBP1#, DSTBN1#

D[47:32]#, DBI2# DSTBP2#, DSTBN2#

D[63:48]#, DBI3# DSTBP3#, DSTBN3#

1 2 ... 15 16 17 18 19 20 21 22 23 24 25 ... 101 102

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